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hm514100d series 4,194,304-word 1-bit dynamic ram ade-203-680a (z) rev. 1.0 nov. 13, 1997 description the hitachi hm514100d is a cmos dynamic ram organized 4,194,304 word 1-bit. hm514100d has realized higher density, higher performance and various functions by employing 0.8 m m cmos process technology and some new cmos circuit design technologies. the hm514100d offers fast page mode as a high speed access mode. multiplexed address input permits the hm514100d to be packaged in standard 300-mil 26-pin plastic soj. features single 5 v ( 10%) access time : 60 ns/70 ns/80 ns (max) power dissipation ? active mode : 605 mw/550 mw/495 mw (max) ? standby mode : 11 mw (max) 0.55 mw (max) (l-version) fast page mode capability refresh cycles ? 1024 refresh cycles: 16 ms : 128 ms (l-version) 3 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? hidden refresh test function battery backup operation (l-version)
hm514100d series 2 ordering information type no. access time package hm514100ds-6 hm514100ds-7 hm514100ds-8 60 ns 70 ns 80 ns 300-mil 26-pin plastic soj (cp-26/20d) HM514100DLS-6 hm514100dls-7 hm514100dls-8 60 ns 70 ns 80 ns
hm514100d series 3 pin arrangement 1 2 3 4 5 9 10 11 12 13 din we ras nc a10 a0 a1 a2 a3 v cc v dout cas nc a9 a8 a7 a6 a5 a4 ss 26 25 24 23 22 18 17 16 15 14 hm514100ds series (top view) pin description pin name function a0 to a10 address input row address a0 to a10 column address a0 to a10 refresh address a0 to a9 din data-in dout data-out ras row address strobe cas column address strobe we read/write enable v cc power supply v ss ground nc no connection
hm514100d series 4 block diagram 256 k memory array mat i/o bus & column decoder 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat i/o bus & column decoder i/o bus & column decoder i/o bus & column decoder 256 k memory array mat i/o bus & column decoder 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat i/o bus & column decoder i/o bus & column decoder i/o bus & column decoder row driver row driver row driver row driver row driver row driver row driver row driver row decoder & peripheral circuit we ras cas row driver row driver row driver row driver row driver row driver row driver row driver row address buffer column address buffer address a0?10 ras control circuit cas control circuit we control circuit din i/o buffer dout
hm514100d series 5 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C1.0 to +7.0 v supply voltage relative to v ss v cc C1.0 to +7.0 v short circuit output current iout 50 ma power dissipation p t 1.0 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to +70 c) parameter symbol min typ max unit note supply voltage v ss 000v v cc 4.5 5.0 5.5 v 1 input high voltage v ih 2.4 6.5 v 1 input low voltage v il C1.0 0.8 v 1 note: 1. all voltage referred to v ss .
hm514100d series 6 dc characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) hm514100d -6 -7 -8 parameter symbol min max min max min max unit test conditions notes operating current i cc1 110 100 90 ma ras , cas cycling t rc = min 1, 2 standby current i cc2 2 2 2 ma ttl interface ras , cas = v ih dout = high-z 1 1 1 ma cmos interface ras , cas 3 v cc C 0.2 v dout = high-z standby current (l-version) i cc2 100 100 100 m a cmos interface ras , cas = v ih we , address and din = v ih or v il dout = high-z 4 ras -only refresh current i cc3 110 100 90 ma t rc = min 2 standby current i cc5 5 5 5 ma ras = v ih , cas = v il dout = enable 1 cas -before- ras refresh current i cc6 110 100 90 ma t rc = min fast page mode current i cc7 110 100 90 ma t pc = min 1, 3 battery backup current (standby with cbr refresh) (l- version) i cc10 200 200 200 m at rc = 125 m s t ras 1 m s we = v ih , cas = v il oe address, din = v ih or v il dout = high-z 4 input leakage current i li C10 10 C10 10 C10 10 m a 0 v vin 7 v output leakage current i lo C10 10 C10 10 C10 10 m a 0 v vout 7 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc 2.4 v cc v high iout = C5 ma output low voltage v ol 0 0.4 0 0.4 0 0.4 v low iout = 4.2 ma notes: 1. i cc depends on output load condition when the device is selected. i cc max is specified at the output open condition. 2. address can be changed twice or less while ras = v il . 3. address can be changed once or less while cas = v ih . 4. v cc C 0.2 v v ih 6.5 v and 0 v v il 0.2 v.
hm514100d series 7 capacitance (ta = 25 c, v cc = 5 v 10%) parameter symbol typ max unit notes input capacitance (address, data-in) c i1 5 pf 1 input capacitance (clocks) c i2 7 pf 1 output capacitance (data-out) c o 7 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. ras , cas = v ih to disable dout. ac characteristics (ta = 0 to +70 c, v cc = 5 v 10%, v ss = 0 v) *1, *12, *15 test conditions input rise and fall time : 5 ns input timing reference levels : 0.8 v, 2.4 v output load : 2 ttl gate + c l (100 pf) (including scope and jig) read, write, read-modify-write and refresh cycles (common parameters) hm514100d -6 -7 -8 parameter symbol min max min max min max unit notes random read or write cycle time t rc 110 130 150 ns ras precharge time t rp 40 50 60 ns ras pulse width t ras 60 10000 70 10000 80 10000 ns 18 cas pulse width t cas 15 10000 20 10000 20 10000 ns 19 row address setup time t asr 0 0 0 ns row address hold time t rah 10 10 10 ns column address setup time t asc 0 0 0 ns column address hold time t cah 15 15 15 ns ras to cas delay time t rcd 20 45 20 50 20 60 ns 8 ras to column address delay time t rad 15 30 15 35 15 40 ns 9 ras hold time t rsh 15 20 20 ns cas hold time t csh 60 70 80 ns cas to ras precharge time t crp 10 10 10 ns transition time (rise and fall) t t 350 350 350 ns7 refresh period t ref 16 16 16 ms refresh period (l-version) t ref 128 128 128 ms
hm514100d series 8 read cycle hm514100d -6 -7 -8 parameter symbol min max min max min max unit notes access time from ras t rac 60 70 80 ns 2, 3, 16 access time from cas t cac 15 20 20 ns 3, 4, 14, 16 access time from address t aa 30 35 40 ns 3, 5, 14, 16 read command setup time t rcs 0 0 0 ns read command hold time to cas t rch 0 0 0 ns17 read command hold time to ras t rrh 0 0 0 ns17 column address to ras lead time t ral 30 35 40 ns output buffer turn-off time t off 015020020ns6 write cycle hm514100d -6 -7 -8 parameter symbol min max min max min max unit notes write command setup time t wcs 0 0 0 ns10 write command hold time t wch 15 15 15 ns write command pulse width t wp 10 10 10 ns write command to ras lead time t rwl 15 20 20 ns write command to cas lead time t cwl 15 20 20 ns data-in setup time t ds 0 0 0 ns11 data-in hold time t dh 15 15 15 ns 11 read-modify-write cycle hm514100d -6 -7 -8 parameter symbol min max min max min max unit notes read-modify-write cycle time t rwc 130 155 175 ns ras to we delay time t rwd 60 70 80 ns 10 cas to we delay time t cwd 15 20 20 ns 10 column address to we delay time t awd 30 35 40 ns 10
hm514100d series 9 refresh cycle hm514100d -6 -7 -8 parameter symbol min max min max min max unit notes cas setup time (cbr refresh cycle) t csr 10 10 10 ns cas hold time (cbr refresh cycle) t chr 10 10 10 ns ras precharge to cas hold time t rpc 10 10 10 ns cas precharge time in normal mode t cpn 10 10 10 ns fast page mode cycle hm514100d -6 -7 -8 parameter symbol min max min max min max unit notes fast page mode cycle time t pc 40 45 50 ns fast page mode cas precharge time t cp 10 10 10 ns fast page mode ras pulse width t rasc 100000 100000 100000 ns 13 access time from cas precharge t acp 35 40 45 ns 3, 14, 16 ras hold time from cas precharge t rhcp 35 40 45 ns fast page mode read-modify-write cycle hm514100d -6 -7 -8 parameter symbol min max min max min max unit notes fast page mode read-modify-write cycle time t pcm 60 70 75 ns cas precharge to we delay time t cpw 35 40 45 ns 10
hm514100d series 10 test mode cycle hm514100d -6 -7 -8 parameter symbol min max min max min max unit notes test mode we setup time t ws 0 0 0 ns test mode we hold time t wh 10 10 10 ns notes: 1. ac measurements assume t t = 5 ns. 2. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 3. measured with a load circuit equivalent to 2 ttl loads and 100 pf. 4. assumes that t rcd 3 t rcd (max) and t rad t rad (max). 5. assumes that t rcd t rcd (max) and t rad 3 t rad (max). 6. t off (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih and v il . 8. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only, if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . 9. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only, if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 10. t wcs , t rwd , t cwd , t awd and t cpw are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only; if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t rwd 3 t rwd (min), t cwd 3 t cwd (min), t awd 3 t awd (min) and t cpw 3 t cpw (min) , the cycle is a read-modify- write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. these parameters are referred to cas leading edge in an early write cycle and to we leading edge in a delayed write or read-modify-write cycle. 12. an initial pause of 100 m s is required after power up followed by a minimum of eight initialization cycles ( ras -only refresh cycle or cas -before- ras refresh cycle). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles is required. 13. t rasc defines ras pulse width in fast page mode cycles. 14. access time is determined by the longest among t aa , t cac and t acp . 15. test mode operation specified in this data sheet is 8-bit test function controlled by control address bits - - - ra10, ca10 and ca0. this test mode operation can be performed by we -and- cas -before- ras (wcbr) refresh cycle. refresh during test mode operation will be performed by normal read cycles or by wcbr refresh cycles. when the state of eight test bits accord each other, the condition of the output data is high level. when the state of test bits do not accord, the condition of the output data is low level. data output pin is dout and data input pin is din. in order to end this test mode operation, perform a cas -before- ras refresh cycle or a ras -only refresh cycle.
hm514100d series 11 16. in a test mode read cycle, the value of t rac , t aa , t cac and t acp is delayed for 2 ns to 5 ns for the specified value. these parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 17. either t rch or t rrh must be satisfied 18. t ras (min) = t rwd (min) + t rwl (min) + t t in read-modify-write cycle. 19. t cas (min) = t cwd (min) + t cwl (min) + t t in read-modify-write cycle. 20. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hm514100d series 12 timing waveforms *20 read cycle ras cas address we dout t ras t rc t rp t csh t rcd t rsh t cas t ral t cah t rad t t asr rah t asc t rcs t rch t rrh t cac t off t aa t rac t t t crp row column dout
hm514100d series 13 early write cycle ras cas address we din dout t rc t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t ds t dh din * t wcs wcs (min) high-z* t
hm514100d series 14 delayed write cycle address cas ras we din dout t ras t rc t rp t csh t crp t rcd t rsh t cas t asr t rah t asc t cah row column t rcs t wp t rwl t cwl t ds t dh din invalid dout t off t t
hm514100d series 15 read-modify-write cycle din dout we address cas ras t ras t rwc t rp t crp t t t rcd t cas t rad t asr t rah t cah t asc row column t cwd t rcs t awd t rwd t wp t cwl t rwl t ds t dh din dout t cac t aa t off t rac
hm514100d series 16 ras -only refresh cycle cas ras address t rc t ras t rp t t t crp t rpc t crp t asr t rah row high-z dout
hm514100d series 17 cas -before- ras refresh cycle ras cas we address dout t rc t rp t ras t rp t rpc t t t cpn t csr t chr t cpn t rpc t crp t ws t wh t off1 high-z
hm514100d series 18 hidden refresh cycle address we dout cas ras t rc t rc t rc t rp t ras t rp t ras t rp t ras t t t rsh t chr t t rcd t rad t ral t cah t asc t rah t asr row column t rcs t cac t aa t rac dout t off (refresh) (read) (refresh) t cas t rrh t rch crp t chr t crp
hm514100d series 19 fast page mode read cycle address we dout cas ras t rasc t rhcp t rp t t t csh t pc t rsh t rcd t cas t cp t cas t cp t cas t crp t rad t ral t asr t rah t cah t cah t cah t asc t asc row column t rch t rrh t rcs t rch t rch t rcs t rcs t cac t aa t rac t acp t acp t aa t aa dout t off t cac t off t cac t off t asc dout dout column column
hm514100d series 20 fast page mode early write cycle ras cas address we din dout t rasc t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah row t wcs t wcs t wcs t wch t wch t wch t ds t dh t ds t dh t ds t dh din din din high-z column column column * t wcs wcs (min) t
hm514100d series 21 fast page mode delayed write cycle din we address ras dout cas t rasc t rp t t t csh t pc t rsh t cas t rcd t cp t cas t cp t cas t crp t asr t rah t asc t t asc t cah t asc t cah row column column column t t rcs tt wp t cwl t cwl t t t t ds t t ds t dh din din din t off t off t off invalid dout t rwl t rcs wp cah t rcs wp cwl dh ds dh invalid dout invalid dout
hm514100d series 22 fast page mode read-modify-write cycle dout din we address cas ras t rasc t rp t t t pcm t rcd t cas t cp t cas t cp t cas t crp t t cah t asr t rah t asc t asc t asc row column t rcs t rad t awd t awd t rcs t rcs t rwl t cwl t cwl t t awd t wp t wp t wp t cwd t cpw t cwd t t ds t ds ds t dh t dh t dh din din t cac t cac t cac t aa t acp t acp t rac t aa t aa t off t off off dout dout dout cah cwd cpw t rwd din t cwl t t t cah column column
hm514100d series 23 test mode cycle cbr or ras -only refresh ras cas we set cycle** test mode cycle *,** reset cycle normal mode ** * address, din: h or l
hm514100d series 24 test mode set cycle we -and- cas -before ras -refresh @@ ?? @@ ?? @@ ?? @@ ?? @@ ?? cas we address dout ras t rc t rp t ras t rp t chr t csr t rpc t rpc t crp t t t cpn t ws t wh t cpn t off high-z * din: h or l
hm514100d series 25 package dimensions hm514100ds/dls series (cp-26/20d) 16.90 17.27 max 0.74 7.62 0.13 8.51 0.13 26 14 1 13 0.10 5.08 0.43 0.10 3.50 0.26 + 0.21 ?0.24 2.40 1.30 max 59 22 18 0.80 +0.25 ?.17 1.27 hitachi code jedec eiaj weight (reference value) cp-26/20d conforms conforms 0.6 g 0.41 0.08 unit: mm dimension including the plating thickness base material dimension 6.79 + 0.19 ?0.18
hm514100d series 26 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi america, ltd. semiconductor & ic div. 2000 sierra point parkway brisbane, ca. 94005-1835 u s a tel: 415-589-8300 fax: 415-583-4207 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hm514100d series 27 revision record rev. date contents of modification drawn by approved by 0.0 dec. 3, 1996 initial issue t. oono s. suzuki 1.0 nov. 13, 1997 deletion of hm514100dtt series

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